William L. Lynch
27Patents
13h-index
18Co-inventors
74Inventor score
Filing activity: Jul 28, 1994 → Aug 31, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7382787B1 | Packet routing and switching device | Electricity | 245 | Expired |
| US8270401B1 | Packet routing and switching device | Electricity | 110 | Active |
| US5958041A | Latency prediction in a pipelined microarchitecture | Physics | 91 | Expired |
| US7069372B1 | Processor having systolic array pipeline for processing data packets | Electricity | 38 | Expired |
| US6487715B1 | Dynamic code motion optimization and path tracing | Physics | 36 | Expired |
| US5754819A | Low-latency memory indexing method and structure | Physics | 35 | Expired |
| US7554914B1 | System and method for adaptively balancing network traffic over router output ports | Electricity | 32 | Expired |
| US6317810A | Microprocessor having a prefetch cache | Physics | 31 | Expired |
| US5898852A | Load instruction steering in a dual data cache microarchitecture | Physics | 26 | Expired |
| US6078587A | Mechanism for coalescing non-cacheable stores | Physics | 24 | Expired |
| US7418536B2 | Processor having systolic array pipeline for processing data packets | Electricity | 22 | Expired |
| US7453883B1 | Method for compressing route data in a router | Electricity | 18 | Expired |
| US7525904B1 | Redundant packet routing and switching device and method | Electricity | 13 | Expired |
| US6076147A | Non-inclusive cache system using pipelined snoop bus | Physics | 13 | Expired |
| US7450438B1 | Crossbar apparatus for a forwarding table memory in a router | Electricity | 13 | Expired |
| US5878252A | Microprocessor configured to generate help instructions for performing data cache fills | Physics | 12 | Expired |
| US5900018A | Processor-implemented method of controlling data access to shared resource via exclusive access control write-cache | Physics | 11 | Expired |
| US7710991B1 | Scalable packet routing and switching device and method | Electricity | 10 | Expired |
| US6061766A | Non-inclusive cache method using pipelined snoop bus | Physics | 10 | Expired |
| US7852852B2 | Method for compressing route data in a router | Electricity | 9 | Active |
| US6164840A | Ensuring consistency of an instruction cache with a store cache check and an execution blocking flush instruction in an instruction queue | Physics | 9 | Expired |
| US6016532A | Method for handling data cache misses using help instructions | Physics | 7 | Expired |
| US7706386B2 | Fast 2-key scheduler | Electricity | 6 | Active |
| US9094237B2 | Packet routing and switching device | Electricity | 5 | Active |
| US5649126A | Parallel signal bus with reduced miller effect capacitance | Physics | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.