Methods for controlling timing in a logic emulation system
US5649167A · kind A · utility
28Cited by
25References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partitions the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.