Structure and method for multiple-level read buffer supporting optimal throttled read operations by regulating transfer rate
US5649232A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1995 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Apr 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A structure and a method are provided for refilling a block of memory words stored in a cache memory. The structure and method provide a read buffer to optimally match the processor speed with the main memory using read clock enable RdCEn and acknowledge (Ack) signals. The RdCEn signal is provided as each memory word is available from the main memory. The Ack signal is provided to indicate the time at which the processor may empty the read buffer at the processor clock rate without subsequently executing a wait cycle to wait for any remaining memory words in the block to arrive. The benefit of the present invention is obtained without incurring a performance penalty on the single word read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.