Method to form a capacitor having multiple pillars for advanced DRAMS

US5650351A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventor

• Shye-Lin Wu · 東區, TW

Key dates

• Filing date: Jan 11, 1996
• Grant date: Jul 22, 1997
• Expiry date: Jan 11, 2016

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/911

Abstract

A method of fabricating a capacitor having multiple pillars is presented. The invention uses an oxidized hemispherical grain silicon (HSG-Si) layer as a masking layer, in a series of masking steps, to form pillarets on a storage electrode. The method begins by forming a storage electrode having a connection to an active area on the substrate. Next, a cap insulation layer and a cap polysilicon layer are formed over the storage electrode. The cap polysilicon layer has grains and has grain boundaries between the grains. The cap polysilicon layer is oxidized thus forming a thicker oxide layer at the grain boundaries. The oxide layer is dry etched exposing the cap polysilicon layer and leaves a grain boundary oxide covering the grain boundaries. Next, the exposed cap polysilicon layer is etched using the grain boundary oxide as a mask forming a plurality of cap polysilicon layer pillarets. The grain boundary oxide is then removed. Then the cap insulation layer is etched using the cap polysilicon layer pillarets as a mask forming cap oxide pillarets. The cap polysilicon layer pillarets are then removed. The storage electrode node is dry etched using the cap oxide pillarets as a mask form…