Method of performing solder joint analysis of semi-conductor components
US5651493A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1995 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Apr 24, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for analyzing solder joint assemblies in devices such as solder bumped silicon chips, ball grid arrays or land grid arrays is disclosed. The method includes applying a dye solution to a device under test and then causing that dye solution to penetrate any interstices between any solder interconnect and the device under test, which also includes penetrating any fractures in any joints or joint failures. Next, the dye is dried or cured so as to provide ready analysis upon the analysis portion of the method. The device under test is then caused to be separated or fractured in such a way that a seam or border of a solder joint or an attachment border may be analyzed to identify any structural failure by visually analyzing where any dye has penetrated such structural failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.