Method for controlling the etch profile of an aperture formed through a multi-layer insulator layer
US5652172A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1996 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Apr 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76804
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an aperture with a uniform void-free sidewall etch profile through a multi-layer insulator layer. There is formed upon a semiconductor substrate a multi-layer insulator layer which has a minimum of a first insulator layer and a second insulator layer. The second insulator layer is formed upon the first insulator layer. There is then etched through a first etch method a first aperture completely through the second insulator layer. The first etch method has: (1) a first perpendicular etch selectivity ratio for the second insulator layer with respect to the first insulator layer of at least about 4:1; and (2) a lateral:perpendicular etch selectivity ratio for the second insulator layer of from about 0.5:1 to about 1:1. The first aperture is then etched through a second etch method to form a second aperture completely through the second insulator layer and the first insulator layer. The second etch method has: (1) a second perpendicular etch selectivity ratio for the second insulator layer with respect to the first insulator layer of no greater than about 2:1; and (2) a lateral etch selectivity ratio of the second insulator layer with respect to the first insulator…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.