Nonvolatile memory device
US5652448A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 1996 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Aug 2, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/49
Abstract
The gate structure for a nonvolatile memory device comprising an EEPROM and a latch transistor is fabricated on a substrate by patterning the EEPROM's floating gate in a first polysilicon layer, patterning the EEPROM's control gate over the floating gate in a second polysilicon layer, and then collectively patterning the second and first layers to form the latch transistor's stacked gate. The stacked gate includes a thin gate that is electrically connected to the EEPROM floating gate and a protective layer over and electrically isolated from the thin gate. The stacked gate design eliminates unwanted polysilicon spacers between the latch transistor's channel and its drain and source regions, which improves the control of the memory device. The protective layer prevents ion penetration during the implantation of the latch transistor's drain and source regions. The fabrication process and thinness of the latch transistor gate improve the linewidth control of other transistors formed on the substrate and the latch transistor by avoiding overetching and reducing the normal etching time for the latch gate, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.