Multi-stage pipeline architecture for motion estimation block matching
US5652625A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1996 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Jun 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/10016
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for implementing motion estimation block matching for video image processing. The apparatus receives pixel data of original and compared image blocks for comparison, to obtain an image motion vector. The apparatus has a multi-stage pipelined tree-architecture that includes a computation stage, a summation section, an accumulation stage, and a minimum value evaluation stage. The computation stage includes 2.sup.n computation members for producing a difference error value and a sign bit of the compared image blocks. The summation section coupled at the pipelined stage next to the computation stage, includes a series of summation stages for producing an absolute error value of the compared image blocks. A following accumulation stage adds an output of the single adder means of the last summation stage and a last un-added sign bit, for producing a sum. A last minimum value evaluator evaluates and generates the minimum of the output of the accumulation stage, as the motion vector for the implementation of motion estimation block matching for video image processing. Only a single adder is required in each of the computation members to reduce both the complexity and the proce…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.