Command encoded delayed clock generator
US5652733A · kind A · utility
28Cited by
4References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1996 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Apr 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock feeding circuit to a semiconductor memory wherein the memory is comprised of separate independent control circuits each requiring a clock signal, comprising apparatus for receiving a control signal applied to one of the control circuits, and apparatus for applying a clock signal to the one of the independent control circuits, restricted to the one of the independent control circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.