CMOS static logic circuit
US5654651A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 1995 |
| Grant date | Aug 5, 1997 |
| Priority date | — |
| Expiry date | Oct 18, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A static logic circuit employs pull-down type logic gates having logic transistors forming a power supply current path and logic transistors forming a grounding current path and having current drive abilities higher than those of the logic transistors forming the power supply current path, and pull-up type logic gates having logic transistors forming a power supply current path and logic transistors forming a grounding current path and having current drive abilities lower than the logic transistors forming the power supply current path, and comprises logic series formed by alternately cascading the two types of the logic gates. The static logic circuit is provided with signal merged logic circuits each of which provides a signal having a high speed falling transient and a high speed rising transient by merging the output signals of the logic series.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.