Method and structure for improving patterning design for processing
US5654897A · kind A · utility
7Cited by
5References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1995 |
| Grant date | Aug 5, 1997 |
| Priority date | — |
| Expiry date | Dec 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.