System and method for handling stale data in a multiprocessor system
US5655103A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1995 |
| Grant date | Aug 5, 1997 |
| Priority date | — |
| Expiry date | Feb 13, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for identifying which incoming write data is valid and for insuring that stale data does not overwrite valid data within system memory within a symmetrical multiprocessor data processing system. Upon receipt of a Load Miss request from a processor, a stale bit is established and set equal to zero. A determination is then made of which other processor has ownership of the requested cache line. The requested cache line is then transferred in a cache-to-cache transfer from the second processor to the first processor. If the first processor further modifies the cache line and writes back the cache line to system memory before the original owner of the cache line writes back the stale data with an acknowledgment of the cache-to-cache transfer, the stale bit is set to one. Upon receipt from the acknowledgment from the original owner of the cache line, the stale data is dropped when it is determined that the stale bit has been set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.