Flash memory system, and methods of constructing and utilizing same
US5656837A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 1996 |
| Grant date | Aug 12, 1997 |
| Priority date | — |
| Expiry date | Apr 16, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transistor structure (10), memory array (150) using the transistor structure, and method for making it are presented. The memory array (150), on a semiconductor substrate (152), contains a plurality of substantially parallel bit lines (154,155). A plurality of channel regions in the substrate (152) are bounded in one direction by a sets of bit line pairs (154,155). A conductive field shield layer (160), over a first insulation layer (156), is patterned to provide electrical regions over the channel regions between the first alternate sets of the bit lines (154,155) to form isolation transistor structures when biased with respect to the substrate (152). The field shield layer (160) is patterned to expose the channel regions of the memory transistors (151, . . . , 151'") between second alternate sets of the bit lines (155,154). A second insulating layer (163) is formed over the field shield layer (160). A nonvolatile memory dielectric layer (165) is formed over the channel regions between the second alternate sets of the bit lines (155,154). A conductive gate layer (166), patterned to provide a plurality of stripes, extends across the channel regions of the second alternate sets of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.