Architecture for FPGAs
US5656949A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1995 |
| Grant date | Aug 12, 1997 |
| Priority date | — |
| Expiry date | Dec 29, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable circuit apparatus having a programmable circuit and an input/output circuit with a first terminal is provided. The programmable circuit apparatus includes a programming circuit, with a bus junction, for programming the programmable circuit. The programmable circuit apparatus further includes an isolation circuit having an isolation input, coupled to the first terminal, and an isolation output, coupled to the bus junction of the programming circuit. The isolation circuit further has an isolation control gate which can receive a control signal and in response to that signal, the control gate controllably couples the isolation input to the isolation output. The programmable circuit apparatus also includes an apparatus for testing the routing, the programming circuitry, and the programmable circuit with a minimal impact on the performance of the programmable circuit. The programmable circuit apparatus also has the ability to program three or more antifuses or other programmable elements simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.