Method and apparatus for testing digital to analog and analog to digital converters
US5659312A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1996 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Jun 14, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus suitable for built in self test (BIST) of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) embedded in a mixed-signal integrated circuit, and high precision converters. Deterministic test patterns, such as a binary count, are applied to the DAC, and via the DAC directly to the ADC or via an analog circuit to be tested in the test mode. The testing is performed digitally via the digital-analog-digital path, is compatible with conventional digital test, and requires minimal additional circuitry to implement. The output response of the ADC is accumulated into four or more signatures which individually represent a number of parameters including offset, gain, second harmonic distortion, third harmonic distortion, and differential non-linearity. Also, the four accumulated sums are used to calculate easily the coefficients of a third order polynomial which best fits a set of data points which are the digital output signals expressed as a function of the input test pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.