LogicVision, Inc.
🏢 View company profile →56Patents
3Active
56Granted
39Portfolio score
Filing activity: Jun 14, 1996 → May 24, 2006 · 3 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6829730B2 | Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same | Physics | 141 | Expired |
| US6442722B1 | Method and apparatus for testing circuits with multiple clocks | Physics | 115 | Expired |
| US5923676A | Bist architecture for measurement of integrated circuit delays | Physics | 95 | Expired |
| US6000051A | Method and apparatus for high-speed interconnect testing | Physics | 83 | Expired |
| US6327684A | Method of testing at-speed circuits having asynchronous clocks and controller for use therewith | Physics | 61 | Expired |
| US6204694A | Programmable clock signal generation circuits and methods for generating accurate, high frequency, clock signals | Physics | 58 | Expired |
| US6671839B1 | Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith | Physics | 56 | Expired |
| US6586921B1 | Method and circuit for testing DC parameters of circuit input and output nodes | Physics | 56 | Expired |
| US5659312A | Method and apparatus for testing digital to analog and analog to digital converters | Electricity | 55 | Expired |
| US6363520B1 | Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification | Physics | 52 | Expired |
| US5900753A | Asynchronous interface | Physics | 50 | Expired |
| US6510534B1 | Method and apparatus for testing high performance circuits | Physics | 45 | Expired |
| US6396889B1 | Method and circuit for built in self test of phase locked loops | Electricity | 38 | Expired |
| US6760874B2 | Test access circuit and method of accessing embedded test controllers in integrated circuit modules | Physics | 36 | Expired |
| US6330681A | Method and apparatus for controlling power level during BIST | Physics | 36 | Expired |
| US7370251B2 | Method and circuit for collecting memory failure information | Physics | 35 | Expired |
| US6536008B1 | Fault insertion method, boundary scan cells, and integrated circuit for use therewith | Physics | 35 | Expired |
| US6492798B2 | Method and circuit for testing high frequency mixed signal circuits with low frequency signals | Physics | 34 | Expired |
| US6115827A | Clock skew management method and apparatus | Physics | 34 | Expired |
| US5812469A | Method and apparatus for testing multi-port memory | Physics | 30 | Expired |
| US6745359B2 | Method of masking corrupt bits during signature analysis and circuit for use therewith | Physics | 30 | Expired |
| US6211803A | Test circuit and method for measuring switching point voltages and integral non-linearity (INL) of analog to digital converters | Electricity | 25 | Expired |
| US6615392B1 | Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby | Physics | 25 | Expired |
| US6834361B2 | Method of testing embedded memory array and embedded memory controller for use therewith | Physics | 24 | Expired |
| US6678875B2 | Self-contained embedded test design environment and environment setup utility | Physics | 24 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.