Method for programming redundancy registers in a row redundancy integrated circuitry for a semiconductor memory device, and row redundancy integrated circuitry
US5659509A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1995 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Feb 16, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/789
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming non-volatile row redundancy memory registers. Each register is associated with a respective pair of redundancy row and each one programmable to store in two subsets of a set of memory cells a pair of addresses of a respective pair of adjacent defective rows. Each memory register is supplied with row address signals and with a respective selection signal belonging to a set of column address signals. The method provides for: applying to the row address lines the address of a first defective row of the pair of adjacent defective rows; activating one of the selection signals for selecting the register which is to be programmed; applying to a further column address line a first logic level to select for programming in the selected memory register, a first subset of memory cells; enabling the programming of the address of the first defective row of the pair of adjacent defective rows into the first subset of memory cells; applying to at least a subset of the row address lines the address of the second defective row of the pair; applying to the further column line a second, opposite logic level to select for programming, in the selected memory register, at least a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.