Cache coherency in a multiprocessing system
US5659708A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1994 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Oct 3, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor system utilizing a plurality of bus devices coupled via a shared bus utilizes a specially coded signal to notify a bus device initiating a read or a read with intent to modify operation that the requested data, or cache line, is in a modified state within a cache of another bus device. Unlike the modified response signal, this special signal is sent along with the requested data from the one bus device to the requesting bus device, indicating that this data has priority over any data being sent from the memory system coupled to the shared bus. The present invention allows for cache-to-cache and cache-to-memory-and-cache operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.