Process for fabricating a semiconductor integrated circuit device having the multi-layered fin structure
US5661061A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 27, 1995 |
| Grant date | Aug 26, 1997 |
| Priority date | — |
| Expiry date | Mar 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
A process for forming an upper-layer fin and a lower-layer fin of a storage electrode, and a semiconductor integrated circuit device fabricated by the process. When two-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower-layer fin by the dry-etching method using a first mask, the upper polycrystalline silicon film is patterned at first so far as to form the clearance of the upper-layer fins with the minimum working size of the memory cells of a DRAM, to form the upper-layer fin. Next, the lower-layer fin is formed by the dry-etching method using a second mask which has a pattern enlarged in self-alignment from the pattern of the first mask, so that it is given a larger horizontal size than that of the upper-layer fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.