Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation
US5661662A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Aug 26, 1997 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.