Programmable ABIST microprocessor for testing arrays with two logical views
US5661732A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1995 |
| Grant date | Aug 26, 1997 |
| Priority date | — |
| Expiry date | Dec 14, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test system). The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be used with dual logical views to reduce test time. The ABIST generates pseudo-random address patterns for improved test coverage. A jump-to-third pointer control command enables branching to perform looping after a background has been filled. A data register is divided into multiple sections to enable a Walking/Marching pattern to be executed individually and concurrently in the dual views to further reduce test times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.