Semiconductor device having an SOI structure of mesa isolation type and manufacturing method therefor
US5663588A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1995 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | Jul 11, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device of SOI structure formed by the mesa isolation method, which can sufficiently reduce the wiring capacitance even if the width of the isolation trench is large. An SOI layer which constitutes an element region is formed by forming a buried oxide film in a silicon substrate, forming an isolation trench in the buried oxide film and burying an isolating material in the isolation trench. By the formation of the SOI layer with the isolating material, a dummy SOI layer is formed in a field part other than the element region. Then, by the formation of a MOSFET gate wiring on the dummy SOI layer, the wiring capacitance is reduced. Furthermore, the dummy SOI layer is completely depleted when the MOSFET threshold value is applied to the gate wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.