Internal timing method and circuit for programmable memories
US5663921A · kind A · utility
56Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 21, 1995 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | Feb 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit includes a variable, asymmetrical propagation line composed of a succession of elementary delay elements enabled or disabled on the basis of memorized logic signals, the state of which is determined when debugging the memory in which the circuit is implemented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.