System and method for minimizing simultaneous switching during scan-based testing
US5663966A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 1996 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | Jul 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for reducing simultaneous switching during scan-based testing of a system logic design. System logic is divided into clusters of system logic, and one or more scan chains are associated with each logic cluster. Each of the logic clusters are concurrently scan tested, yet circuitry in the scan chains associated with a cluster are triggered at different times than the circuitry in the scan chains of other clusters. Offset scan control signals provide the triggering for the scan chains of different clusters. Release and capture functions are also controlled to reduce simultaneous release and capture switching in different clusters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.