Steven M. Douskey
78Patents
11h-index
65Co-inventors
81Inventor score
Filing activity: Nov 13, 1989 → Dec 8, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6115763A | Multi-core chip providing external core access with regular operation function interface and predetermined service operation services interface comprising core interface units and masters interface unit | Physics | 240 | Expired |
| US6158032A | Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof | Physics | 98 | Expired |
| US5617430A | Testing system interconnections using dynamic configuration and test generation | Physics | 75 | Expired |
| US5717701A | Apparatus and method for testing interconnections between semiconductor devices | Physics | 62 | Expired |
| US6807645B2 | Method and apparatus for implementing enhanced LBIST diagnostics of intermittent failures | Physics | 45 | Expired |
| US6735543B2 | Method and apparatus for testing, characterizing and tuning a chip interface | Physics | 28 | Expired |
| US5663966A | System and method for minimizing simultaneous switching during scan-based testing | Physics | 18 | Expired |
| US5668816A | Method and apparatus for injecting errors into an array built-in self-test | Physics | 16 | Expired |
| US7114109B2 | Method and apparatus for customizing and monitoring multiple interfaces and implementing enhanced fault tolerance and isolation features | Physics | 16 | Expired |
| US6195775A | Boundary scan latch configuration for generalized scan designs | Physics | 15 | Expired |
| US9404969B1 | Method and apparatus for efficient hierarchical chip testing and diagnostics with support for partially bad dies | Physics | 11 | Active |
| US4972414A | Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (LSSD) system | Physics | 10 | Expired |
| US8856720B2 | Test coverage of integrated circuits with masking pattern selection | Physics | 9 | Active |
| US9103879B2 | Test coverage of integrated circuits with test vector input spreading | Physics | 8 | Active |
| US8407542B2 | Implementing switching factor reduction in LBIST | Physics | 8 | Active |
| US9116205B2 | Test coverage of integrated circuits with test vector input spreading | Physics | 7 | Active |
| US9355203B2 | Shared channel masks in on-product test compression system | Physics | 6 | Active |
| US7793184B2 | Lowering power consumption during logic built-in self-testing (LBIST) via channel suppression | Physics | 5 | Active |
| US7310278B2 | Method and apparatus for in-system redundant array repair on integrated circuits | Physics | 5 | Expired |
| US8667431B1 | Test coverage of integrated circuits with masking pattern selection | Physics | 5 | Active |
| US6448835B1 | High-speed leaf splitter for clock gating | Electricity | 5 | Expired |
| US9032256B2 | Multi-core processor comparison encoding | Physics | 4 | Active |
| US9110135B2 | Chip testing with exclusive OR | Physics | 4 | Active |
| US7915929B2 | High-speed leaf clock frequency-divider/splitter | Physics | 3 | Active |
| US8898530B1 | Dynamic built-in self-test system | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.