Input/output (I/O) holdoff mechanism for use in a system where I/O device inputs are fed through a latency introducing bus
US5664213A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 1995 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | Jul 20, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle. The bus controller responds to a request from a host system for a current value on a first request pin of the I/O device by forwarding to the host system a current value for a voltage on the indicated request pin, as indicated by the deserializer, when the deserializer i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.