Data processing with adaptable external burst memory access
US5664230A · kind A · utility
10Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 1995 |
| Grant date | Sep 2, 1997 |
| Priority date | — |
| Expiry date | May 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing device includes a data processing core (43), a cache (33) connected to the core and having a cache width, and a bus (31) for receiving from an information source external to the data processing device a burst of information having a width which exceeds the cache width by a width difference. The cache is coupled to the bus to receive and store a first portion of the burst which is equal in width to the cache width. A storage circuit (35) is coupled to the bus to receive and store a second portion of the burst corresponding to the width difference, and the storage circuit has an output coupled to the core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.