Semiconductor device checking method
US5665610A · kind A · utility
6Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 17, 1996 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | May 17, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2831
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A plated layer made of a metal which is hard to oxidize is formed on the surface of a check electrode of a semiconductor chip which is formed on a semiconductor wafer. A bump of a contactor is caused to come in contact with the check electrode on which the plated layer is formed in the direction perpendicular to the semiconductor chip. Then, a voltage is applied to the bump of the contactor to make a check such as burn-in on the semiconductor chip in a lump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.