Four transistor SRAM process

US5665629A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Bomy Chen · Cupertino, US
• Gorden Seth Starkey, Jr. · South Burlington, US

Key dates

• Filing date: Aug 11, 1995
• Grant date: Sep 9, 1997
• Expiry date: Aug 11, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/15

Abstract

A SRAM cell with cross-coupled transistors, a pair of transfer gate transistors and a pair of load resistors is manufactured by forming a plurality of field effect transistors in a silicon substrate. In one embodiment, the transistors are formed in an SOI substrate to improve soft-error resistance. An insulator layer is deposited over the source, drain and gate contacts (device contact areas), hole openings are etched into the insulating layer to expose a plurality of device contact areas. A highly resistive layer is patterned to substantially cover and in contact with some selected contact hole openings and device contact areas. A conductive material is deposited into all of the contact hole openings so as to substantially over-fill the contact hole openings and make electrical contact with the device contacts and patterned resistive layer. A planarizing process used to remove the conductive material and the resistive layer outside of the contact holes, thus forming all contact studs with selected studs having integrated resistors. The contact studs are interconnected among themselves and connected to a power bus, a ground, word and bit lines to form the SRAM cell.