Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal
US5665639A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1994 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Feb 23, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A rapid thermal anneal (RTA) process minimizes the intermixing of materials between a bump and a bonding pad so as to provide for a more reliable and durable interconnect between the bump and the bonding pad and so as to allow the probing of wafers prior to bumping. A barrier layer is formed over the bonding pads of devices formed over a semiconductor substrate. Bumps are then formed over the bonding pads and are annealed for a short time at a high temperature so as to soften the bumps for later assembly in a semiconductor package. As a result of this quick annealing process, the intermixing of materials between the bumps and the bonding pads is minimized. This is so despite any decreased step coverage of the barrier layer over probe marks on the bonding pads which resulted from testing the wafer. Accordingly, wafers may now be tested prior to bumping, thus saving the cost, time, and process steps typically incurred in bumping wafers having a zero or low yield of properly functioning semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.