Heuristic prefetch mechanism and method for computer system
US5666505A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 1994 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Mar 11, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A heuristic prefetch mechanism that fetches code without solicitation by the execution unit. The prefetch mechanism is configured to normally prefetch sequential code and, if a particular line of requested code is out of sequence with respect to an immediately preceding line of requested code, is configured to store in a memory tag unit the address of the previous instruction along with the subsequently requested out-of-sequence address. If the execution unit later issues another request for the previous instruction, the prefetch mechanism prefetches the corresponding out-of-sequence address stored in the memory tag unit. During each instruction fetch, a comparison is made to determine whether that particular instruction has been stored within the memory tag unit. If the memory tag unit has stored a non-sequential address corresponding to a requested instruction, the non-sequential address is loaded into a prefetch address latch. If no corresponding entry is in the memory tag unit, the address sequential to the requested address is stored within the prefetch address latch. A memory fetch unit subsequently prefetehes the line corresponding to the address within the prefetch address …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.