Cache memory containing extra status bits to indicate memory regions where logging of data should occur
US5666514A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 1994 |
| Grant date | Sep 9, 1997 |
| Priority date | — |
| Expiry date | Jul 1, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a digital computer memory cache organization for efficient data logging, log-based copy and rollback, high-performance I/O, network switching and multi-cache consistency maintenance. The cache organization implements efficient selective cache write-back, mapping and transferring of data. Write or store operations to cache lines tagged as logged are written through to a log block builder associated with the cache. Non-logged store operations are handled local to the cache, as in a writeback cache. The log block builder combines write operations into data blocks and transfers the data blocks to a log splitter. A log splitter demultiplexes the logged data into separate streams based on address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.