Method for fabricating a dual-gate dielectric module for memory with embedded logic technology
US5668035A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1996 |
| Grant date | Sep 16, 1997 |
| Priority date | — |
| Expiry date | Jun 10, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
Abstract
A method for fabricating a dual-gate oxide for memory with embedded logic has been achieved. The method is described for forming a thin gate oxide for the peripheral circuits on a DRAM device, while providing a thicker oxide for the memory cells having a boosted word line architecture. The method avoids applying photoresist directly to the gate oxide, and thereby prevents contamination. A first gate oxide is formed on the device areas on the substrate. A first polysilicon layer is deposited and patterned leaving portions over the memory cell areas. The first gate oxide is removed over the peripheral device areas, and is replaced by a thinner second gate oxide. A second polysilicon layer is deposited and patterned to remain over the peripheral device areas. The first and second polysilicon layers, having essentially equal thicknesses, are coated with an insulating layer. The FET gate electrodes for both the peripheral and memory cell areas are simultaneously patterned from the first and second polysilicon layers to complete the DRAM structure up to and including the gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.