One step smooth cylinder surface formation process in stacked cylindrical DRAM products
US5668038A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1996 |
| Grant date | Sep 16, 1997 |
| Priority date | — |
| Expiry date | Oct 9, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A method of fabrication of a DRAM cell, which forms an improved smooth top cylinder surface and provides controllable cylinder height. A semiconductor structure is provided having a transistor. Also provided are a barrier layer 12 over a first insulating layer 11 on the semiconductor structure. A polysilicon plug 14 extends through the barrier layer 12 and the insulating layer 11. A second insulating layer 16 is formed over portions of the barrier layer 12 and has an opening over the polysilicon plug 14 and over portions of the barrier layer adjacent to the polysilicon plug 14. A polysilicon layer 18 is formed over the second insulating layer 16, the sidewalls of the second insulating layer 16, the portions of the barrier layer 12 adjacent to the polysilicon plug 14 and over the polysilicon plug 14. A gap filling third insulating layer 20 is formed over the polysilicon layer 18. In an important process, potions of the gap filling third insulating layer 20 and the polysilicon layer 18 are etched back in an one step etch process to form a polysilicon cylinder 22. The critical one step etch processes is comprised of two stages: (1) an insulating layer etch stage and (2) a polysilicon …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.