Method and apparatus for injecting errors into an array built-in self-test
US5668816A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1996 |
| Grant date | Sep 16, 1997 |
| Priority date | — |
| Expiry date | Aug 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved method and apparatus are provided for injecting errors in an array built-in self-test (ABIST) for an array in an integrated circuit driven by at least one controller. The error generation and insertion apparatus is used with the ABIST and includes registers that are set for selecting error injection; for selecting a predetermined ABIST test pattern; and for selecting an address in the array for injecting an error in the predetermined ABIST test pattern. An ABIST pattern is compared with the selected predetermined ABIST test pattern, and the selected address in the array for injecting the error is compared with an ABIST address for the ABIST pattern. The ABIST data is inverted responsive to the selected address in the array for injecting the error equal to the ABIST address. A single bit error or a multiple bit error is selected for an address or all addresses of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.