Process for manufacturing high-density MOS-technology power devices
US5670392A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 30, 1995 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Jun 30, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing high-density MOS-technology power devices includes the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; forming an insulating material layer over the insulated gate layer; selectively removing the insulating material layer and the underlying insulated gate layer to form a plurality of elongated windows having two elongated edges and two short edges, delimiting respective uncovered surface stripes of the semiconductor material layer; implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows and orthogonal to the semiconductor material layer surface, and which are substantially symmetrically tilted at a first prescribed angle with respect to a direction orthogonal to the semiconductor material layer surface, the first angle depending on the overall thickness of the insulated gate layer and of the insulating material layer to prevent the first dopant from being implanted in a central stripe of the uncovered surface stripes, to form pairs of heavily doped elongated source r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.