Ferroelectric memory device
US5671174A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1995 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Dec 19, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The ferroelectric memory device includes (A) at least one memory cell array, the memory cell array including (a) a plurality of memory cells arranged in row and column directions, each of the memory cells having a capacitive element and a transistor, the capacitive element having a ferroelectric film interposed between electrodes facing to each other, storing and retaining binary data in accordance with polarization of the ferroelectric film, one of a source and a drain of the transistor being electrically connected to one of the electrodes of the capacitive element, and (b) a plate line being electrically connected to the other of the electrodes of the capacitive element; and (B) an arrangement for arranging a voltage of the plate line to be fixed and activating the transistor so as to arrange a voltage at a junction of the transistor and the capacitive element to be the same as the voltage of the plate line. The ferroelectric memory device in accordance with the invention accomplishes higher speed operation and lower consumption of electric power, prevents destruction of stored data, and simplifies voltage control and operation control of word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.