Data encryptor having a scalable clock
US5671284A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1996 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Apr 16, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for encrypting and decrypting digital data. The digital data is initially latched by an input register. Sixteen separate cipher stages cascaded in series are used to encrypt the digital data. These cipher stages are operating at a maximum frequency limited only by the process technology. The encoded digital data from the last cipher stage is stored in an output register. The input and output registers are capable of being docked at an interface frequency that is different from that of the DES core's data frequency. After an appropriate number of cycles have elapsed, the output register is sampled. A programmable counter is used to indicate when the output register contains valid encrypted data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.