Alternating data valid control signals for high performance data transfer
US5671370A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1996 |
| Grant date | Sep 23, 1997 |
| Priority date | — |
| Expiry date | Mar 25, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method which utilizes a unique bus protocol in conjunctions plural Dval.sub.-- control signals to minimize the dead time between blocks of data being transferred between components is a data processing system. The present invention introduces another latch-to-latch data valid control signal and alternates the usage of this signal during back to back data transfers from the same or different bus devices. In this manner the restore and tristate dead cycles are totally overlapped with the data transfer and the minimum possible number of dead cycle(s) is achieved between different blocks of data transfers. With the method of the present invention, data providers alternately activate the Dval.sub.-- signals and data receivers look at all Dval.sub.-- signals and if any one of them is active, then the data is considered valid and can be read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.