Field effect transistor having impurity regions of different depths and manufacturing method thereof
US5672533A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1995 |
| Grant date | Sep 30, 1997 |
| Priority date | — |
| Expiry date | Nov 9, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0221
Abstract
Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.