Self-defining instruction size
US5673409A · kind A · utility
4Cited by
12References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1993 |
| Grant date | Sep 30, 1997 |
| Priority date | — |
| Expiry date | Mar 31, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for defining, in a computing system, the bit size of an instruction to be executed by a processing unit. Instructions are realized in the form of a plurality of memory location devices. At least one of said memory location devices, in a predetermined position, is established as a MODE bit. The MODE bit assumes a first value indicative of parallel instruction execution and assumes a second value indicative of non-parallel instruction execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.