Method for etching a conducting layer of the step-covered structure for semiconductor fabrication
US5674354A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1995 |
| Grant date | Oct 7, 1997 |
| Priority date | — |
| Expiry date | Sep 29, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32137
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for etching a conducting layer in a semiconductor device fabrication procedure is disclosed. The method provides for the formation of the conductor path with defined and precise control over the path width. The fabricated semiconductor device has a step-raised layer-covering structural configuration on a substrate, and the step-raised layer-covering structural configuration forms re-entrances when an insulation layer is formed over the step-raised layer-covering structure and the portion of the substrate surrounding the structure. The method includes forming a conducting layer on the insulation layer and then forming a shielding mask on the conducting layer for defining a conducting path with a predetermined pattern. The method further includes applying an anisotropic etching process for removing portions of the conducting layer not covered by the shielding mask. The method also forms residual stringers of the conducting layer in the re-entrances. The method then applies an anisotropic etching process to form first protecting layers covering the sidewalls of the conducting path, as well as second protecting layers covering the stringers, wherein the first protecting layers…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.