Channel accelerated tunneling electron cell, with a select region incorporated, for high density low power applications

US5675161A · kind A · utility

Inventor

• Mammen Thomas · Seattle, US

Key dates

• Filing date: Mar 28, 1995
• Grant date: Oct 7, 1997
• Expiry date: Mar 28, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/685

Abstract

Improved non-volatile memory cells capable of being written and erased electrically, suitable for high density low voltage applications are disclosed. Writing the cells is by using the Channel Accelerated Carrier Tunneling (CACT) method for programming memories, (patent application Ser. No. 08/209,787 filed on Mar. 11, 1994) and the erase is by tunneling through a thin oxide region. Two structural embodiments are disclosed. First embodiment, Trenched-Channel Accelerated Tunneling Electron cell (Tr.sub.-- CATE), and a second embodiment Trench Wall-Channel Accelerated Tunneling Electron cell (Tw-CATE), both make use of separate regions of the channel for write and erase and hence provide high reliability of operation. The cells disclosed use a vertical step etch to form part of the channel to accelerate the carriers and also to act as a select gate without increasing the cell area. By separating the portion of the gate on the side wall from that over the surface, along a continuous channel between the source and drain, independently operating storage region and a select/accelerating region are formed along the same channel. This structure allows independent voltages to be applied to …