Method and circuit for testing memories in integrated circuit form
US5675539A · kind A · utility
6Cited by
3References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1995 |
| Grant date | Oct 7, 1997 |
| Priority date | — |
| Expiry date | Dec 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory that contains a device for the precharging and reading of the bit lines, including a precharging element, a current-voltage converter and a read circuit, further contains a test circuit to isolate the output of the converter from the precharging element and from the read circuit, to apply a test voltage to a cell of the memory through the converter and to measure the current in the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.