Non-volatile memory system having internal data verification test mode
US5675540A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 22, 1996 |
| Grant date | Oct 7, 1997 |
| Priority date | — |
| Expiry date | Jan 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including means for verifying the contents of a memory cell contained in a memory array to determine if a shift in the threshold voltage level has occurred. The memory system is placed into a test mode of operation in which an internal program or erase verify operation is executed under the control of the system's internal state machine. Once in the mode, the memory system steps through each memory cell, address by address, and reads the contents of the cell using the appropriate reference voltage for a programming or erase operation. A status register bit is set indicating successful completion of the verification operation for a block of memory cells. A register bit is also set if a cell fails the verification operation. This provides a more accurate determination of the state of a memory cell than can be achieved by performing an external read operation using read operation or data verification reference voltage levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.