Method for transmitting information over an intelligent low power serial bus
US5675811A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1995 |
| Grant date | Oct 7, 1997 |
| Priority date | — |
| Expiry date | Aug 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch in a base station (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Data and commands are sent from the base station to a peripheral device, and data is received from the peripheral device by the base station by configuring each peripheral device on the bus to receive data and clock signals from the base station in an idle mode of operation. Upon a command send being transmitted by the base station, all peripheral devices on the serial bus between the base station and an addressed peripheral device remain in the idle mode and the addressed peripheral device is connected to the bus so that clock and data signals on the bus to are passed to the peripheral device. When the peripheral devices on the bus are in the idle mode of operation, and the base station transmits a command get to an addressed peripheral device, the addressed peripheral device and all peripheral devices between the addressed peripheral device and the base statio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.