John E. Watkins
41Patents
17h-index
49Co-inventors
81Inventor score
Filing activity: Feb 6, 1976 → Dec 31, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6453360B1 | High performance network interface | Electricity | 273 | Expired |
| US6480489B1 | Method and apparatus for data re-assembly with a high performance network interface | Electricity | 156 | Expired |
| US5793993A | Method for transmitting bus commands and data over two wires of a serial bus | Physics | 139 | Expired |
| US5983332A | Asynchronous transfer mode (ATM) segmentation and reassembly unit virtual address translation unit architecture | Electricity | 102 | Expired |
| US5675811A | Method for transmitting information over an intelligent low power serial bus | Physics | 93 | Expired |
| US5247648A | Maintaining data coherency between a central cache, an I/O cache and a memory | Physics | 75 | Expired |
| US5119290A | Alias address support | Physics | 70 | Expired |
| US5854911A | Data buffer prefetch apparatus and method | Electricity | 67 | Expired |
| US5263142A | Input/output cache with mapped pages allocated for caching direct (virtual) memory access input/output data based on type of I/O devices | Physics | 65 | Expired |
| US5937436A | Network interface circuit including an address translation unit and flush control circuit and method for checking for invalid address translations | Physics | 53 | Expired |
| US6049857A | Apparatus and method for translating addresses utilizing an ATU implemented within a network interface card | Electricity | 35 | Expired |
| US5845325A | Virtual address write back cache with address reassignment and cache block flush | Physics | 35 | Expired |
| US5991854A | Circuit and method for address translation, using update and flush control circuits | Physics | 29 | Expired |
| US7610431B1 | Configuration space compaction | Physics | 28 | Expired |
| US5325717A | Adjustable measuring device | Physics | 26 | Expired |
| US5161162A | Method and apparatus for system bus testability through loopback | Physics | 20 | Expired |
| US10593574B2 | Techniques for combining CMP process tracking data with 3D printed CMP consumables | Electricity | 17 | Active |
| US5448913A | Adjustable measuring device | Physics | 15 | Expired |
| US4055935A | Clutch brake mechanism for lawnmowers | Human Necessities | 14 | Expired |
| US6105110A | Circuit and method for replacement of address translations | Physics | 11 | Expired |
| US8312187B2 | Input/output device including a mechanism for transaction layer packet processing in multiple processor systems | Physics | 9 | Active |
| US6073224A | Network interface circuit with replacement circuitry and method for segregating memory in an address translation unit with locked and unlocked regions | Physics | 8 | Expired |
| US7836328B1 | Method and apparatus for recovering from system bus transaction errors | Physics | 7 | Active |
| US7124319B2 | Delay compensation for synchronous processing sets | Electricity | 6 | Expired |
| US8312461B2 | System and method for discovering and protecting allocated resources in a shared virtualized I/O device | Physics | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.