Method and apparatus for performing memory cell verification on a nonvolatile memory circuit
US5677879A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1996 |
| Grant date | Oct 14, 1997 |
| Priority date | — |
| Expiry date | Oct 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for verifying the status of selected nonvolatile memory cells of an integrated memory circuit, such as during a memory erase or programming operation, and an integrated nonvolatile memory circuit including circuitry for performing this verification method. Preferably, the invention employs simple logic circuitry including a flip-flop to assert successful verification data only in response to a continuous validity of a verification signal throughout a sampling period, thereby avoiding false assertion of successful verification data. The sampling period is preferably longer than the expected duration of fluctuations due to noise in the verification signal. During the sampling period of a verification operation, the logic circuitry receives a raw verification signal indicative of the instantaneous relation between a measured threshold voltage of a selected memory cell and a reference voltage. The raw verification signal is valid if the threshold voltage has a desired relation to the reference voltage at an instant of time. The flip-flop remains in a first state while the raw verification signal is valid, but enters a second state in response to the raw verification signal goi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.