FET with gate spacer
US5679589A · kind A · utility
25Cited by
13References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1992 |
| Grant date | Oct 21, 1997 |
| Priority date | — |
| Expiry date | Apr 3, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A semiconductor integrated circuit structure and method of fabrication is disclosed. The structure includes a FET gate with adjacent double or triple layered gate spacers. The spacers permit precise tailoring of lightly doped drain junction profiles having deep and shallow junction portions. In addition, a self-aligned silicide may be formed solely over the deep junction portion thus producing a reliable low contact resistance connection to source and drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.