CMOS integrated circuit with reduced susceptibility to PMOS punchthrough

US5682051A · kind A · utility

Assignee

• Dallas Semiconductor Corporation · US

Inventor

• Thomas E. Harrington, III · Los Altos, US

Key dates

• Filing date: Jun 7, 1995
• Grant date: Oct 28, 1997
• Expiry date: Jun 7, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/859

Abstract

A CMOS integrated circuit, in which the PMOS devices each include a buried channel region (26). The P+ source/drain regions (54) and (56) are separated from the channel region (26) by N-type lateral field isolating regions (58) and (60). Whenever a voltage negative enough to turn on the channel is applied, the isolating regions will be inverted by the electric fields from the comers of the gate. Thus, the value of the transistor's threshold voltage is not changed. However, these lateral field isolating regions provide an electric field modification which helps to minimize drain-induced barrier lowering, and thereby reduces the leakage current of the device in the off state. Preferably the lateral field isolating regions are formed by a doping which is maximal at the same depth (below the gate oxide) at which the threshold-voltage-adjust doping of the channel is maximal. The preferred CMOS process provides lateral field isolating regions on the PMOS devices, and also provides LDD regions on the NMOS devices. The lateral field isolating regions in the PMOS transistors are formed by a blanket N-type implant, and the LDD regions in the NMOS transistors are formed by a patterned implant…